library ieee;
use ieee.std_logic_1164.all;
....

entity name_same_with_filename is
	port ( -- the ports opened for the users
		input_1	: in std_logic; -- std_logic have more than states '1' and '0'
        ...
        result	: out std_logic -- PortName : <mode> <type>
        -- the last port is not followed by a ';'
	);
end entity; -- remember the ';'

architecture arch_name of entity_name is
    -- signal declarations(used for internal connections)
   	signal name	: bit;
    -- constant
begin
    -- behavioral of the system
end architecture;

library ieee;
use ieee.std_logic_1164.all;
 
entity example_and is
  port (
    input_1    : in  std_logic;
    input_2    : in  std_logic;
    and_result : out std_logic
    );
end example_and;
 
architecture rtl of example_and is
  signal and_gate : std_logic;
begin
  and_gate   <= input_1 and input_2;
  and_result <= and_gate;
end rtl;

library ieee;
use ieee.std_logic_1164.all;


entity test is
	port (
		i_clock : in std_logic;
		q1, q2, q3, q4 : out std_logic
	);
end test;


architecture rtl of test is

	signal test1 : std_logic := '1';
	signal test2 : std_logic := '0';
	signal test3 : std_logic := '0';
	signal test4 : std_logic := '0';

begin
		
	flip : process (i_clock) is
	begin
		if rising_edge(i_clock) then
			test2 <= test1;
			test3 <= test2;
			test4 <= test3;
		end if;
	end process flip;
    
    -- or without a name
            
    -- process (i_clock)
	-- begin
	-- 	if rising_edge(i_clock) then
	-- 		test2 <= test1;
	-- 		test3 <= test2;
	-- 		test4 <= test3;
	-- 	end if;
	-- end process;
	
	q1 <= test1;
	q2 <= test2;
	q3 <= test3;
	q4 <= test4;
	
end rtl;

library ieee;
use ieee.std_logic_1164.all;

entity uPC is
	port(
		LOAD : in std_logic;
		CPuPC  : in std_logic;
		E   : in std_logic;
		CLR  : in std_logic;
		D    : in std_logic_vector(15 downto 0);
		Q    : out std_logic_vector(15 downto 0)
	);
end entity uPC;


architecture rtl of uPC is
	
	COMPONENT f74161 -- f74161是Quartus library所带的74161的bdf文件，实质上在图形界面里使用的是它的一个子部件调用，还有一个p74161，貌似是根据device family来选择两者，具体的细节不太了解。
	PORT -- 声明port
	(
		CLRN		:	 IN STD_LOGIC;
		LDN		:	 IN STD_LOGIC;
		D		:	 IN STD_LOGIC;
		C		:	 IN STD_LOGIC;
		B		:	 IN STD_LOGIC;
		ENP		:	 IN STD_LOGIC;
		A		:	 IN STD_LOGIC;
		ENT		:	 IN STD_LOGIC;
		CLK		:	 IN STD_LOGIC;
		RCO		:	 OUT STD_LOGIC;
		QD		:	 OUT STD_LOGIC;
		QC		:	 OUT STD_LOGIC;
		QB		:	 OUT STD_LOGIC;
		QA		:	 OUT STD_LOGIC
	);
END COMPONENT;
	
	signal rco_wire : std_logic_vector(2 downto 0);
	signal useless: std_logic; -- 实例化的时候有一个输出管脚没有用到，但我不太会设置这个空管脚，就直接写了一个没有用到的信号
	
begin

    -- 以下都是f74161的实例化，需要设置port map，里面signal的顺序就是上面声明时port的顺序
	counter0 : f74161 port map(CLR, LOAD, D(3), D(2), D(1), E, D(0), E, CPuPC, rco_wire(0), Q(3), Q(2), Q(1), Q(0));
	counter1 : f74161 port map(CLR, LOAD, D(7), D(6), D(5), rco_wire(0), D(4), rco_wire(0), CPuPC, rco_wire(1), Q(7), Q(6), Q(5), Q(4));
	counter2 : f74161 port map(CLR, LOAD, D(11), D(10), D(9), rco_wire(1), D(8), rco_wire(1), CPuPC, rco_wire(2), Q(11), Q(10), Q(9), Q(8));
	counter3 : f74161 port map(CLR, LOAD, D(15), D(14), D(13), rco_wire(2), D(12), rco_wire(2), CPuPC, useless, Q(15), Q(14), Q(13), Q(12));
	
	
end rtl;